1. Field of the Invention
The present invention relates to storage devices and semiconductor apparatuses, and more particularly, to a storage device and a semiconductor apparatus that include memory cells each including a storage element storing and holding information in accordance with an electric resistance state.
2. Description of the Related Art
In information apparatuses, such as computers, high-density dynamic random access memories (DRAMs) with high operation speed are widely used as random access memories (RAMs).
However, since DRAMs are volatile memories, which lose information when the power is turned off, nonvolatile memories, which hold information even after the power is turned off, are desired.
Thus, ferroelectric random access memories (FeRAMs), magnetic random access memories (MRAMs), phase change memories, and resistance change memories, such as programmable metallization cells (PMCs) and resistance random access memories (RRAMs), are suggested as promising nonvolatile memories.
Such nonvolatile memories are capable of holding written information for a long time without supplying power. In addition, since a refresh operation is not necessary for nonvolatile memories, the power consumption can be reduced.
The resistance change nonvolatile memories, such as PMCs and RRAMs, have a relatively simple configuration in which a material having a characteristic in that the resistance changes by application of a voltage or a current is used for a storage layer storing and holding information and in which a voltage or a current is applied to two electrodes provided so as to sandwich the storage layer therebetween. Thus, miniaturization of a storage element can be easily achieved.
PMCs have a configuration in which an ionic conductor containing a predetermined metal is sandwiched between two electrodes, and the metal contained within the ionic conductor is also contained within one of the two electrodes. Thus, PMCs utilize a characteristic in which an electrical characteristic of the ionic conductor, such as resistance or capacitance, changes when a voltage is applied across the two electrodes.
More specifically, the ionic conductor is made of a solid solution of chalcogenide and metal (for example, amorphous GeS or amorphous GeSe), and one of the two electrodes contains Ag, Cu, or Zn (see, for example, PCT Japanese Translation Patent Publication No. 2002-536840).
A configuration of an RRAM, for example, in which a polycrystalline PrCaMnO3 thin film is sandwiched between two electrodes and in which the resistance of the PrCaMnO3 thin film, which is a recording film, greatly changes in accordance with application of voltage pulses or current pulses to the two electrodes is described, for example, in “Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)” written by W. W. Zhuang et al. in Technical Digest “International Electron Devices Meeting”, 2002, p. 193. A voltage pulse whose polarity changes depending on recording (writing) or erasing of information is applied.
Another configuration of an RRAM, for example, in which SrZrO3 into which a small amount of Cr is doped (monocrystal or polycrystal) is sandwiched between two electrodes and in which the resistance of a recording film changes in accordance with currents flowing from the electrodes is described, for example, in “Reproducible Switching Effect in Thin Oxide Films for Memory Applications” written by A. Beck et al., in Applied Physics Letters, 2000, vol. 77, p. 139-141.
In this document, a current-voltage (I-V) characteristic of the storage layer is described, and threshold voltages in recording and erasing are ±0.5 V. With this configuration, information can be recorded and erased in accordance with application of voltage pulses. Necessary pulse voltages are ±1.1 V and a necessary voltage pulse width is 2 milliseconds. In addition, recording and erasing can be performed at high speed, and an operation can be performed with a voltage pulse width of 100 nanoseconds. In this case, necessary pulse voltages are ±5 V.
However, under the present situation, it is difficult for FeRAMs to perform nondestructive reading. Since FeRAMs perform destructive reading, the reading speed of FeRAMs is slow. In addition, since there is a restriction on the number of times polarization reversal according to reading or recording can be performed, the number of rewritable times is limited.
MRAMs use a magnetic field for recording, and a current flowing through wiring generates the magnetic field. Thus, a large amount of current is necessary for recording.
Phase change memories, which perform recording by application of voltage pulses with the same polarity and different sizes, perform switching depending on temperature. Thus, phase change memories are susceptible to changes in the ambient temperature.
In the PMC described in PCT Japanese Translation Patent Publication No. 2002-536840, the crystallization temperature of amorphous GeS or amorphous GeSe is about 200° C., and a characteristic is deteriorated when an ionic conductor is crystallized. Thus, the PMC does not endure high temperature in an actual process for manufacturing a storage element, for example, a process for forming a chemical vapor deposition (CVD) insulating film or a protection film.
A material of a storage layer suggested for the RRAM described in each of the document titled “Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)” and the document titled “Reproducible Switching Effect in Thin Oxide Films for Memory Applications” is crystalline. Thus, processing at a temperature of about 600° C. is necessary, it is extremely difficult to manufacture monocrystal of the suggested material, and miniaturization is difficult due to the influence of grain boundary when polycrystal is used.
In addition, although recording and erasing of information performed by application of pulse voltages is suggested for the above-described RRAMs, the resistance of the storage layer after recording changes depending on the pulse width of the applied pulse voltage in the suggested configurations. In addition, the fact that the resistance after recording depends on the pulse width for the recording indirectly indicates that the resistance changes even when the same pulse is repeatedly applied.
For example, as reported in the document titled “Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)”, when pulses with the same polarity are applied, the resistance after recording greatly changes depending on the pulse width. When the pulse width is shorter, such as less than 50 nanoseconds, the resistance change ratio by recording is lower. When the pulse with is longer, such as more than 100 nanoseconds, instead of being saturated at a constant value, a resistance closer to the resistance before recording is acquired as the pulse width increases. In addition, the document titled “Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)” describes features of the memory configuration in which a storage layer is connected in series with a metal-oxide semiconductor (MOS) transistor for access control and in which the storage layer and the MOS transistor are disposed in an array form. When the pulse width changes within a range between 10 nanoseconds and 100 nanoseconds, the resistance of the storage layer after recording changes depending on the pulse width. If the pulse width is much longer, it is predicted, from the characteristic of the storage layer, that the resistance decreases again.
In other words, RRAMs have a feature in which the resistance after recording depends on the size of a pulse voltage and a pulse width. Thus, variations in the size of the pulse voltage and in the pulse width cause variations in the resistance after recording.
Thus, a pulse voltage with a pulse width shorter than about 100 nanoseconds has a lower resistance ratio by recording and is susceptible to variations in the resistance after recording. Thus, it is difficult to perform stable recording.
Thus, when recording is performed using such a pulse voltage with a shorter pulse width, it is necessary to perform a process for verifying the content of information after recording is performed, in order to reliably perform recording.
For example, before recording, a process for reading and verifying the content of information that has already been recorded in a storage element (the resistance of a storage layer) is performed. Then, recording is performed so as to correspond to the relationship between the verified content (resistance) and the content (resistance) to be recorded. Alternatively, for example, after recording, a process for reading and verifying the content of information recorded in the storage element is performed. If the verified resistance is different from a desired resistance, re-recording is performed to correct the verified resistance to the desired resistance.
Thus, a longer period of time is spent for recording, and, for example, it is difficult to perform overwriting of data or the like at high speed.
In order to solve such problems, a storage device is suggested, for example, in Japanese Patent Application No. 2004-22121. In the storage device, a memory cell includes a storage element having a characteristic in which the resistance changes in accordance with application of a voltage of a threshold level or higher across both ends and a circuit element that is connected in series with the storage element and that serves as a load. The storage device has a characteristic in which, when the voltage applied across ends of the storage device and the circuit element is the threshold level or higher, the combined resistance of the storage element and the circuit element of the memory cell after the resistance of the storage element changes from a higher state to a lower state is substantially constant irrespective of the size of the voltage. Such a storage device realizes a stable recording operation, and reduces the period of time necessary for recording of information.
When an operation for changing the resistance of the storage element from a higher state to a lower state is defined as “writing” and an operation for changing the resistance of the storage element from the lower state to the higher state is defined as “erasing”, a particular procedure for performing erasing on a plurality of memory cells from a memory array of, for example, the resistance change storage device described in Japanese Patent Application No. 2004-22121 is not available. Thus, erasing is performed by access to each bit.
An example of an erasing sequence of a known procedure is described next. In this example, a storage element on which erasing is performed by application of a voltage (erasing voltage) of about 0.5 V across ends of the storage element and a circuit element (access transistor) is described.
In the erasing sequence of the known procedure, first, an address to be erased is set, and a bit line provided in the column direction and a word line provided in the row direction are determined. Then, a potential difference of 0.5 V or more is generated across a selected memory cell. Then, as a gate voltage of an access transistor of the selected memory cell, a voltage of Vth or more (Vth is the minimum voltage at which an inversion layer starts to be formed on a channel region surface by application of the gate voltage) is applied, and an erasing voltage necessary for erasing is generated across the memory cell. After erasing is performed on the memory cell by application of the erasing voltage to the memory cell, the gate voltage of the access transistor of the memory cell is reduced to less than Vth. Accordingly, erasing is completed. Then, in order to perform erasing on another memory cell, another memory address is set, and erasing on the memory cell is performed, as in the sequence described above.
More specifically, referring to FIG. 8, an example in which erasing is performed on a memory cell a, a memory cell b, a memory cell c, and so on in that order will be described. FIG. 9 is a schematic diagram for explaining the potential of each word line. In the initial state, the potential of all the word lines is 0 V.
Referring to FIG. 8, in order to perform erasing on the memory cell a, a potential of 0 V is applied to a bit line B0, a potential of 1 V is applied to the other bit lines (B1, B2, . . . , and Bn), and a potential of 1 V is applied to a source line S. In such a state, at time t1, a potential of Vth or more is applied to a word line W0, and a potential difference of 1.0 V is generated across the memory cell a. Accordingly, erasing on the memory cell a starts. At time t2, which is after the lapse of about 20 nanoseconds from time t1 (erasing ends by time t2), the potential of the word line W0 is returned to 0 V, and erasing on the memory cell a is completed.
Then, in order to perform erasing on the memory cell b, at time t3, a potential of Vth or more is applied to a word line W1, and a potential difference of 1.0 V is generated across the memory cell b. Accordingly, erasing on the memory cell b starts. Then, at time t4, which is after the lapse of about 20 nanoseconds from time t3 (erasing ends by time t4), the potential of the word line W1 is returned to 0 V, and erasing on the memory cell b is completed.
Then, in order to perform erasing on the memory cell c, at time t5, a potential of Vth or more is applied to a word line W2, and a potential difference of 1.0 V is generated across the memory cell c. Accordingly, erasing on the memory cell c starts. Then, at time t6, which is after the lapse of about 20 nanoseconds from time t5 (erasing ends by time t6), the potential of the word line W2 is returned to 0 V, and erasing on the memory cell c is completed.
Similarly, for the bit line B0, erasing on memory cells is sequentially performed.
In addition, in order to perform erasing on memory cells connected to the bit line Bn, a potential of 0V is applied to the bit line Bn, a potential of 1 V is applied to the other bit lines, and a potential of 1 V is applied to the source line S. In such a state, erasing on the memory cells connected to the bit line Bn is performed in accordance with a sequence similar to the erasing procedure for the memory cells connected to the bit line B0.
In FIG. 9, sign “P” represents the electric energy consumed by the memory array. When erasing on a memory cell is performed in accordance with the above-mentioned sequence, predetermined electric energy is consumed immediately (about 1 nanosecond) after a potential difference (erasing voltage) of 1.0 V is generated across the memory cell by application of a potential of Vth or more to a word line, and, after that, hardly any electric energy is consumed. This is because, for a large majority of memory cells, erasing is completed immediately (about 1 nanosecond) after the erasing voltage is applied.
When taking into consideration the fact that, for a large majority of memory cells, erasing is completed by application of an erasing voltage for about 1 nanosecond, that is, when taking into consideration the fact that about 1 nanosecond is spent from application of an erasing voltage to completion of erasing, about 1 nanosecond is sufficient for an application time of an erasing voltage. However, some memory cells spend an erasing time of about 20 nanoseconds. Thus, in order to reliably perform erasing by a single application of an erasing voltage, it is necessary to provide an erasing time of at least about 20 nanoseconds. Thus, an application time of an erasing voltage is about 20 nanoseconds.